Functional Overview
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is
the WATCHDOG.
3.12 Low-Power Modes Block
The low-power modes on the F281x and C281x are similar to the 240x devices. Table 3−17 summarizes the
various modes.
Table 3−17. F281x and C281x Low-Power Modes
†
EXIT
MODE
LPM(1:0)
OSCCLK
CLKIN
SYSCLKOUT
Normal
X,X
on
on
on
−
XRS,
WDINT,
Any Enabled Interrupt,
XNMI
‡
IDLE
0,0
on
on
on
§
Debugger
XRS,
WDINT,
XINT1,
XNMI,
on
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
STANDBY
0,1
1,X
off
off
off
off
(watchdog still running)
SCIRXDB,
CANRX,
Debugger
§
off
XRS,
XNMI,
Debugger
HALT
(oscillator and PLL turned off,
watchdog not functional)
§
†
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not
be exited and the device will go back into the indicated low power mode.
‡
§
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional
while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is
recognized by the processor. The LPM block performs no tasks during
this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
HALT Mode:
Only the XRS and XNMI external signals can wake the device from
HALT mode. The XNMI input to the core has an enable/disable bit.
Hence, it is safe to use the XNMI signal for this function.
NOTE: The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them in when the IDLE instruction was executed.
55
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
