Functional Overview
3.8
OSC and PLL Block
Figure 3−9 shows the OSC and PLL block on the F281x and C281x.
XPLLDIS
Latch
XRS
XF_XPLLDIS
OSCCLK (PLL Disabled)
X1/XCLKIN
XCLKIN
0
1
CLKIN
CPU
SYSCLKOUT
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
4-Bit PLL Select
X2
PLL
4-Bit PLL Select
PLL Block
Figure 3−9. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to the F281x and C281x devices using the
X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the
X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed V
The PLLCR bits [3:0] set the clocking ratio.
.
DD
Table 3−15. PLLCR Register Bit Definitions
†
BIT(S)
NAME
TYPE
XRS RESET
DESCRIPTION
15:4
reserved
R = 0
0:0
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.
Bit Value
n
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed
1
2
3
4
5
6
7
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
Reserved
Reserved
Reserved
Reserved
3:0
DIV
R/W
0,0,0,0
8
9
10
11
12
13
14
15
†
The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.
52
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
