Functional Overview
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3−14.
†
Table 3−14. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
reserved
ADDRESS
SIZE (x16)
DESCRIPTION
0x00 7010
0x00 7017
8
reserved
reserved
HISPCP
LOSPCP
PCLKCR
reserved
LPMCR0
LPMCR1
reserved
PLLCR
0x00 7018
0x00 7019
0x00 701A
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7024
0x00 7025
1
1
1
1
1
1
1
1
1
1
1
1
1
1
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
Peripheral Clock Control Register
Low Power Mode Control Register 0
Low Power Mode Control Register 1
‡
PLL Control Register
SCSR
System Control & Status Register
Watchdog Counter Register
WDCNTR
reserved
WDKEY
Watchdog Reset Key Register
Watchdog Control Register
0x00 7026
0x00 7028
reserved
WDCR
3
1
6
0x00 7029
0x00 702A
0x00 702F
reserved
†
‡
All of the above registers can only be accessed, by executing the EALLOW instruction.
The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not
reset PLLCR.
51
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
