Peripherals
Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
0x00 0C00
0x00 0C01
0x00 0C02
0x00 0C03
0x00 0C04
0x00 0C05
0x00 0C06
0x00 0C07
0x00 0C08
0x00 0C09
0x00 0C0A
0x00 0C0B
0x00 0C0C
0x00 0C0D
0x00 0C0E
0x00 0C0F
0x00 0C10
0x00 0C11
0x00 0C12
0x00 0C13
0x00 0C14
0x00 0C15
0x00 0C16
0x00 0C17
SIZE (x16)
DESCRIPTION
CPU-Timer 0, Counter Register
TIMER0TIM
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
0x00 0C18
0x00 0C3F
reserved
40
58
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
