Peripherals
In the F281x and C281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown
in Figure 4−2.
INT1
to
TINT0
PIE
CPU-TIMER 0
INT12
C28x
CPU-TIMER 1
(Reserved for TI
system functions)
TINT1
INT13
INT14
XINT13
CPU-TIMER 2
(Reserved for
DSP/BIOS)
TINT2
NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal (See Notes A and B)
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value
in the period register “PRDH:PRD”. The counter register, decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed
in Table 4−1 are used to configure the timers. For more information, see the TMS320x281x System Control
and Interrupts Reference Guide (literature number SPRU078).
57
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
