Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
‡
I/O/Z
§
NAME
PU/PD
DESCRIPTION
179-PIN 176-PIN
128-PIN
PBK
GHH
PGF
POWER SIGNALS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
H1
L1
23
37
20
29
42
56
63
74
82
94
102
110
17
26
30
39
−
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
P5
56
P9
75
1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2,
Recommended Operating Conditions, for voltage
requirements.
P12
K12
G12
C14
B10
C8
−
100
112
128
143
154
19
G4
K1
32
SS
L2
38
SS
P4
52
SS
K6
58
SS
P8
70
53
59
62
73
−
SS
M10
L11
K13
J14
G13
E14
B14
D10
C10
B8
78
SS
86
SS
Core and Digital I/O Ground Pins
99
SS
105
113
120
129
142
−
SS
−
SS
88
95
−
SS
SS
SS
103
109
25
49
−
SS
153
31
SS
J4
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
L7
64
L10
N14
G11
E9
81
3.3-V I/O Digital Power Pins
−
−
114
145
83
104
3.3-V Flash Core Power Pin. This pin should be connected to
3.3 V at all times after power-up sequence requirements have
been met. This pin is used as VDDIO in ROM parts and must
be connected to 3.3 V in ROM parts as well.
V
N8
69
52
DD3VFL
†
‡
§
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3.
24
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
