Functional Overview
3
Functional Overview
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
CPU-Timer 2
Real-Time JTAG
External
TINT2
INT14
Control
PIE
Interface
(XINTF)
Address(19)
†
(96 interrupts)
‡
INT[12:1]
TINT1
Data(16)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
INT13
NMI
XINT13
External Interrupt
Control
(XINT1/2/13, XNMI)
XNMI
G
P
I
L0 SARAM
4K x 16
SCIA/SCIB
SPI
FIFO
FIFO
FIFO
L1 SARAM
4K x 16
O
GPIO Pins
McBSP
C28x CPU
M
U
X
eCAN
Flash
128K x 16 (F2812)
128K x 16 (F2811)
64K x 16 (F2810)
EVA/EVB
ROM
128K x 16 (C2812)
128K x 16 (C2811)
64K x 16 (C2810)
12-Bit ADC
16 Channels
System Control
XRS
X1/XCLKIN
X2
RS
§
OTP
(Oscillator and PLL
1K x 16
CLKIN
+
Peripheral Clocking
+
H0 SARAM
8K × 16
XF_XPLLDIS
Low-Power
Modes
+
Memory Bus
Boot ROM
4K × 16
WatchDog)
Peripheral Bus
Protected by the code-security module.
†
‡
§
45 of the possible 96 interrupts are used on the devices.
XINTF is available on the F2812 and C2812 devices only.
On C281x devices, the OTP is replaced with a 1K X 16 block of ROM
Figure 3−1. Functional Block Diagram
28
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
