Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
‡
I/O/Z
§
NAME
PU/PD
DESCRIPTION
179-PIN 176-PIN
128-PIN
PBK
GHH
PGF
ADC ANALOG INPUT SIGNALS (CONTINUED)
ADCINB7
F5
D1
D2
D3
C1
B1
C3
C2
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
I
I
I
I
I
I
I
I
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
8-Channel Analog Inputs for Sample-and-Hold B. The ADC
pins should not be driven before the V , V , and
DDA1 DDA2
pins have been fully powered up.
V
DDAIO
ADC Voltage Reference Output (2 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (2 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
ADCREFP
ADCREFM
E2
E4
11
10
11
10
I/O
I/O
ADC Voltage Reference Output (1 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (1 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
ADCRESEXT
ADCBGREFIN
AVSSREFBG
AVDDREFBG
ADCLO
F2
E6
E3
E1
B3
F3
C5
16
164
12
16
116
12
O
I
ADC External Current Bias Resistor (24.9 kΩ ±±5)
Test Pin. Reserved for TI. Must be left unconnected.
ADC Analog GND
I
13
13
I
ADC Analog Power (3.3-V)
175
15
127
15
I
Common Low Side Analog Input. Connect to analog ground.
ADC Analog GND
V
I
SSA1
SSA2
V
165
117
I
ADC Analog GND
V
V
V
V
V
V
F4
A5
C6
A6
B2
A2
14
166
163
162
1
14
118
115
114
1
I
I
I
I
ADC Analog 3.3-V Supply
ADC Analog 3.3-V Supply
ADC Digital GND
DDA1
DDA2
SS1
ADC Digital 1.8-V (or 1.9-V) Supply
3.3-V Analog I/O Power Pin
Analog I/O Ground Pin
DD1
DDAIO
SSAIO
176
128
†
‡
§
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3.
23
April 2001 − Revised December 2004
SPRS174L