Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
‡
I/O/Z
§
NAME
PU/PD
DESCRIPTION
179-PIN 176-PIN
128-PIN
PBK
GHH
PGF
JTAG
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are
ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal
pulldown device. In a low-noise environment, TRST can be
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
TRST
B12
135
98
I
PD
TCK
TMS
A12
D13
136
126
99
92
I
I
PU
PU
JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising
edge of TCK.
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge
of TCK.
TDI
C13
D12
D11
C9
131
127
137
146
96
93
I
PU
−
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
TDO
EMU0
EMU1
O/Z
I/O/Z
I/O/Z
Emulator pin 0. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
100
105
PU
PU
Emulator pin 1. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
ADC ANALOG INPUT SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
B5
D5
E5
A4
B4
C4
D4
A3
167
168
169
170
171
172
173
174
119
120
121
122
123
124
125
126
I
I
I
8-Channel analog inputs for Sample-and-Hold A. The ADC
pins should not be driven before V , V , and V
pins have been fully powered up.
I
I
I
I
I
DDA1 DDA2 DDAIO
†
‡
§
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3.
22
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
