Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
‡
I/O/Z
§
NAME
PU/PD
DESCRIPTION
179-PIN 176-PIN
128-PIN
PBK
GHH
PGF
XINTF SIGNALS (2812 ONLY) (CONTINUED)
Microprocessor/Microcomputer Mode Select. Switches
between microprocessor and microcomputer mode. When
high, Zone 7 is enabled on the external interface. When low,
Zone 7 is disabled from the external interface, and on-chip
boot ROM may be accessed instead. This signal is latched
into the XINTCNF2 register on a reset and the user can modify
this bit in software. The state of the XMP/MC pin is ignored
after reset.
XMP/MC
F1
17
−
I
PD
External Hold Request. XHOLD, when active (low), requests
the XINTF to release the external bus and place all buses and
strobes into a high-impedance state. The XINTF will release
the bus when any current access is complete and there are no
pending accesses on the XINTF.
XHOLD
E7
159
82
−
−
I
PU
External Hold Acknowledge. XHOLDA is driven active (low)
when the XINTF has granted a XHOLD request. All XINTF
buses and strobe signals will be in a high-impedance state.
XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when
XHOLDA is active (low).
XHOLDA
K10
O/Z
−
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active
(low) when an access to the XINTF Zone 0 or Zone 1 is
performed.
XZCS0AND1
XZCS2
P1
44
88
−
−
−
O/Z
O/Z
O/Z
−
−
−
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an
access to the XINTF Zone 2 is performed.
P13
B13
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active
(low) when an access to the XINTF Zone 6 or Zone 7 is
performed.
XZCS6AND7
133
Write Enable. Active-low write strobe. The write strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.
XWE
XRD
N11
M3
N4
84
42
51
−
−
−
O/Z
O/Z
O/Z
−
−
−
Read Enable. Active-low read strobe. The read strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The XRD
and XWE signals are mutually exclusive.
Read Not Write Strobe. Normally held high. When low, XR/W
indicates write cycle is active; when high, XR/W indicates read
cycle is active.
XR/W
†
‡
§
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3.
20
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
