Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
‡
I/O/Z
§
NAME
PU/PD
DESCRIPTION
179-PIN 176-PIN
128-PIN
PBK
GHH
PGF
XINTF SIGNALS (2812 ONLY) (CONTINUED)
Ready Signal. Indicates peripheral is ready to complete the
access when asserted to 1. XREADY can be configured to be
a synchronous or an asynchronous input. See the timing
diagrams for more details.
XREADY
B6
161
−
I
PU
JTAG AND MISCELLANEOUS SIGNALS
Oscillator Input − input to the internal oscillator. This pin is also
used to feed an external clock. The 28x can be operated with
an external clock source, provided that the proper voltage
levels be driven on the X1/XCLKIN pin. It should be noted that
the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core
X1/XCLKIN
K9
77
58
I
digital power supply (V ), rather than the 3.3-V I/O supply
DD
(V
DDIO
). A clamping diode may be used to clamp a buffered
clock signal to ensure that the logic-high level does not
exceed V (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
DD
X2
M9
F11
A13
76
57
87
97
O
O
I
Oscillator Output
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose clock
source. XCLKOUT is either the same frequency, 1/2 the
frequency, or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be
turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register
to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed
in a high impedance state during reset.
XCLKOUT
TESTSEL
119
134
−
PD
Test Pin. Reserved for TI. Must be connected to ground.
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution.
The PC will point to the address contained at the location
0x3FFFC0. When XRS is brought to a high level, execution
begins at the location pointed to by the PC. This pin is driven
low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS pin will be driven low for the
watchdog reset duration of 512 XCLKIN cycles.
XRS
D6
160
113
I/O
PU
The output buffer of this pin is an open-drain with an internal
pullup (100 µA, typical). It is recommended that this pin be
driven by an open-drain device.
Test Pin. Reserved for TI. On F281x devices, TEST1 must be
left unconnected. On C281x devices, this pin is a “no connect
(NC)” (i.e., this pin is not connected to any circuitry internal
to the device).
TEST1
TEST2
M7
N7
67
66
51
50
I/O
I/O
−
−
Test Pin. Reserved for TI. On F281x devices, TEST2 must be
left unconnected. On C281x devices, this pin is a “no connect
(NC)” (i.e., this pin is not connected to any circuitry internal
to the device).
†
‡
§
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3.
21
April 2001 − Revised December 2004
SPRS174L
TI [ TEXAS INSTRUMENTS ]
