Introduction
2.3
Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) package.
Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3
shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.
2.3.1 Terminal Assignments for the GHH Package
See Table 2−2 for a description of each terminal’s function(s).
CAP6
_QEPI2
T3CTRIP
_PDPINTB
T4CTRIP/
EVBSOC
PWM8
PWM7
V
V
V
V
V
DD
P
N
M
L
XZCS0AND1
SPISOMIA
PWM10
PWM9
XD[8]
XZCS2 SCITXDB
SS
DD
SS
DD
T4PWM
_T4CMP
TEST2
V
V
DDIO
XR/W
C4TRIP
XD[11]
XA[2]
XWE
CANTXA CANRXA
DD3VFL
XD[9]
CAP4
_QEP3
CAP5
_QEP4
SCIRXDB
PWM1
V
SPISIMOA XA[1]
XRD
XD[6]
XD[4]
PWM12
PWM11
TEST1
X2
XA[3]
PWM2
XD[12]
PWM6
SS
V
V
V
V
XD[7]
C5TRIP
TDIRB
XD[10]
PWM3
PWM4
V
DD
DDIO
DDIO
SS
SS
T3PWM
_T3CMP
X1/
XCLKIN
PWM5
V
V
V
V
K
J
SPICLKA
SPISTEA
C6TRIP TCLKINB
XHOLDA
XD[13]
SS
SS
DD
SS
T1PWM
_T1CMP
T2PWM
_T2CMP
V
V
MCLKXA MFSRA
XD[3]
XD[5]
XA[4]
DDIO
SS
CAP1
_QEP1
CAP2
_QEP2
CAP3
_QEPI1
T1CTRIP
_PDPINTA
H
G
F
V
DD
MCLKRA XD[1]
MFSXA
XD[2]
XA[0]
XA[5]
T2CTRIP/
EVASOC
V
V
V
MDXA
MDRA
XD[0]
XA[6]
V
SS
DDIO
SS
DD
ADC-
RESEXT
V
XMP/MC
ADCINB7
C3TRIP XCLKOUT XA[7] TCLKINA TDIRA
V
SSA1
DDA1
AVDD-
REFBG
AVSS-
REFBG
ADC-
BGREFIN
XNMI
_XINT13
V
E
D
C
B
A
ADCREFP
ADCREFM ADCINA5
XHOLD
XA[13]
C2TRIP
EMU0
XA[8]
TDO
C1TRIP
TMS
V
DDIO
SS
XINT2
_ADCSOC _XBIO
XINT1
V
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
XRS
XA[18]
XA[9]
SS
V
V
V
V
V
ADCINB3 ADCINB0 ADCINB1 ADCINA2
SCITXDA
EMU1
XA[15]
XD[15]
XA[12]
XD[14]
XA[10]
TDI
SSA2
SS1
DD
SS
DD
V
V
ADCINB2
ADCLO ADCINA3 ADCINA7 XREADY XA[17]
TRST XZCS6AND7
V
V
DDAIO
SS
SS
DD
XF
_XPLLDIS
TCK
V
ADCINA0 ADCINA4
V
V
SCIRXDA XA[16]
XA[14]
TESTSEL XA[11]
SSAIO
DDA2
DD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 2−1. TMS320F2812 and TMS320C2812 179-Ball GHH MicroStar BGA (Bottom View)
16
SPRS174L
April 2001 − Revised December 2004
TI [ TEXAS INSTRUMENTS ]
