ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
general-purpose I/O (continued)
15
14
12
11
10
9
8
7
4
3
2
1
0
TOUT
R/W
Reserved
DIR3
R/W
DIR2
R/W
DIR1
R/W
DIR0
R/W
Reserved
DAT3 DAT2 DAT1 DAT0
R/W R/W R/W R/W
LEGEND: R = Read, W = Write
Figure 8. General-Purpose I/O Control Register Bit Layout
Table 8. General-Purpose I/O Control Register Bit Functions
BIT
NO.
BIT
NAME
BIT
VALUE
FUNCTION
0
1
X
0
1
X
0
1
Timer output disable. Uses GPIO3 as general-purpose I/O. (Reset value)
15
TOUT
Timer output enable. Overrides DIR3. Timer output is driven on GPIO3 and readable in DAT3.
Register bit is reserved.
14-12 Reserved
GPIOn pin is used as an input. (Reset value)
GPIOn pin is used as an output.
†
11−8
7−4
DIRn
Reserved
Register bit is reserved.
GPIOn is driven with a 0 (DIRn=1). GPIOn is read as 0 (DIRn=0).
GPIOn is driven with a 1 (DIRn=1). GPIOn is read as 1 (DIRn=0).
†
DATn
3−0
†
n = 0, 1, 2, or 3
The TOUT bit is used to multiplex the output of the timer and GPIO3. DIR3 has no affect when TOUT = 1. All
pins are programmable as an input or output via the direction bit (DIRn). Data is either driven or read from the
data bit field (DATn).
GPIO2 is a special case where the logic level determines the operation of BIO-conditional instructions on the
CPU. GPIO2 is always mapped as a general-purpose I/O, but the BIO function exists when this pin is configured
as an input.
hardware timer
Each subsystem of the 5420 features a 16-bit timing circuit with a 4-bit prescaler. The timer counter decrements
by one at every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The
timer can be stopped, restarted, reset, or disabled by specific status bits. The timer output pulse is driven on
GPIO3 when the TOUT bit is set to one in the general-purpose I/O control register. The device must be in HPI
mode (XIO = 0) to drive TOUT on the GPIO3 pin.
software-programmable phase-locked loop (PLL)
The clock generator provides clocks to the 5420 device, and consists of a phase-locked loop (PLL) circuit. The
clock generator requires a reference clock input, which must be provided by using an external clock source. The
reference clock input is then divided by two (DIV mode) to generate clocks for the 5420 device. Alternately, the
PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency
by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The default startup
mode for the PLL on the 5420 device is bypass (multiply-by-1).
The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the
PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once
the PLL is locked, it continues to track and maintain synchronization with the input signal. Only subsystem A
controls the PLL. Subsystem B cannot access the PLL registers.
31
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