ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
memory-mapped registers
Each 5420 subsystem has 27 memory-mapped CPU registers, which are mapped in data memory space
addresses 0h to 1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on 5420. Each
subsystem device also has a set of memory-mapped registers associated with peripherals. Table 10, and
Table 11 show additional peripheral MMRs associated with the 5420.
Table 9. Processor Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DESCRIPTION
DEC
HEX
IMR
IFR
—
0
0
Interrupt Mask Register
Interrupt Flag Register
Reserved for testing
Status Register 0
1
1
2−5
6
2−5
6
ST0
ST1
AL
7
7
Status Register 1
8
8
Accumulator A Low Word (15−0)
AH
AG
BL
9
9
Accumulator A High Word (31−16)
Accumulator A Guard Bits (39−32)
Accumulator B Low Word (15−0)
Accumulator B High Word (31−16)
Accumulator B Guard Bits (39−32)
Temporary Register
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
B
BH
BG
C
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition Register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary Register 0
Auxiliary Register 1
Auxiliary Register 2
Auxiliary Register 3
Auxiliary Register 4
Auxiliary Register 5
Auxiliary Register 6
Auxiliary Register 7
Stack Pointer
BK
Circular Buffer Size Register
Block-Repeat Counter
Block-Repeat Start Address
Block-Repeat End Address
Processor Mode Status Register
Extended Program Counter
Reserved
BRC
RSA
REA
PMST
XPC
—
33
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