ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
DMA controller synchronization events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit
field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event
for a channel. The list of possible events and the DSYN values are shown in Table 5.
Table 5. DMA Synchronization Events
DSYN VALUE
0000b
DMA SYNCHRONIZATION EVENT
No synchronization used
0001b
McBSP0 Receive Event
McBSP0 Transmit Event
McBSP2 Receive Event
McBSP2 Transmit Event
McBSP1 Receive Event
McBSP1 Transmit Event
FIFO Receive Buffer Not Empty Event
FIFO Transmit Buffer Not Full Event
Reserved
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b − 1111b
DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 0, 1, 2, and
3 are multiplexed with other interrupt sources. DMA channels 0 and 1 share an interrupt line with the receive
and transmit portions of McBSP2 (IMR/IFR bits 6 and 7), and DMA channels 2 and 3 share an interrupt line with
the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11). When the 5402 is reset, the interrupts
from these four DMA channels are deselected. The INTSEL bit field in the DMA channel priority and enable
control (DMPREC) register can be used to select these interrupts, as shown in Table 6.
Table 6. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7] IMR/IFR[10] IMR/IFR[11]
BXINT2
BXINT2
DMAC1
BRINT1
DMAC2
DMAC2
BXINT1
DMAC3
DMAC3
10b
11b
Reserved
subsystem communications
The 5420 device provides two options for efficient core-to-core communications:
D
D
Core-to-core FIFO communications
EMIF-to-HPI communications (asynchronous external memory interface-to host-port interface)
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