ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉꢄ ꢅ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢇꢍꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
software-programmable phase-locked loop (PLL) (continued)
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
D
D
PLL mode. The input clock (CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using
the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled by the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD) in subsystem A. The CLKMD register is used to define the clock configuration of the PLL clock
module.
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