ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢄꢅ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢇꢍ ꢂ ꢂꢑ ꢖ
SPRS080F − MARCH 1999 − REVISED OCTOBER 2008
multichannel buffered serial port (McBSP) (continued)
Like the standard serial port interface on the McBSP, the data is communicated to devices interfacing to the
McBSP by way of the data transmit (BDX) pin for transmit and the data receive (BDR) pin for receive. Control
information in the form of clocking and frame synchronization is communicated by way of BCLKX, BCLKR,
BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers accessible
via the internal peripheral bus. The CPU or DMA reads the received data from the data receive register (DRR)
and writes the data to be transmitted to the data transmit register (DXR). Data written to the DXR is shifted out
to BDX by way of the transmit shift register (XSR). Similarly, receive data on the BDR pin is shifted into the
receive shift register (RSR) and copied into the receive buffer register (RBR). RBR is then copied to DRR, which
can be read by the CPU or DMA. This allows internal data movement and external data communications
simultaneously. The control block consists of internal clock generation, frame synchronization signal
generation, and their control, and multichannel selection. This control block sends notification of important
events to the CPU and DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and
REVT.
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmitted data is encoded according to specified companding law and received
data is decoded to 2’s complement format.
The sample rate generator provides the McBSP with several means of selecting clocking and framing for both
the receiver and transmitter. Both the receiver and transmitter can select clocking and framing independently.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory
and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission
and reception. Up to 32 channels in a bit stream consisting of a maximum of 128 channels can be enabled.
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the SPI protocol. Clock stop mode
works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are
programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI
mode, both the transmitter and the receiver operate together as a master or as a slave.
direct memory access unit (DMA)
The 5420 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA allows movements of data to and from internal program/data memory,
internal peripherals, such as the McBSPs and the HPI to occur in the background of the CPU operation. Each
subsystem has its own independent DMA with six programmable channels, allowing six different contexts for
DMA operation. The HPI has a dedicated auxiliary DMA channel. Figure 7 illustrates the memory map
accessible by the DMA.
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
