Electrical Specifications
5.7.2 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer
to the
TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals
(literature number SPRU131) for
detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 5–6.
Table 5–6 and Table 5–7 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 5–4).
Table 5–6. Multiply-By-N Clock Option Timing Requirements
MIN
Integer PLL multiplier N (N = 1–15)†
PLL multiplier N = x.5†
PLL multiplier N = x.25, x.75†
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
Fall time, X2/CLKIN
Rise time, X2/CLKIN
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
20
20
20
MAX
200
100
50
4
4
ns
ns
ns
ns
ns
UNIT
tc(CI)
Cycle time, X2/CLKIN
† N is the multiplication factor.
Table 5–7. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
tc(CO)
td(CI-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
tp
Cycle time, CLKOUT
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
tf(CI)
MIN
8.33
4
7
2
2
H
H
30
11
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ms
tw(CIH)
tc(CI)
X2/CLKIN
td(CI-CO)
tc(CO)
tp
CLKOUT
Unstable
tw(CIL) tr(CI)
tw(COH)
tf(CO)
tw(COL)
tr(CO)
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5–4. Multiply-by-One Clock Timing
November 2001 – Revised July 2003
SPRS007B
63
TI [ TEXAS INSTRUMENTS ]
