Electrical Specifications
5.8
Memory and Parallel I/O Interface Timing
5.8.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5–8 and Table 5–9 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5t
c(CO)
(see Figure 5–5 and Figure 5–6).
Table 5–8. Memory Read Timing Requirements
MIN
Access time, read data access from address
valid, first read access†
For accesses not immediately following a
HOLD operation
For read accesses immediately following a
HOLD operation
MAX
4H–9
4H–11
2H–9
7
0
UNIT
ns
ns
ns
ns
ns
ta(A)M1
ta(A)M2
tsu(D)R
Access time, read data access from address valid, consecutive read accesses†
Setup time, read data valid before CLKOUT low
th(D)R
Hold time, read data valid after CLKOUT low
† Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5–9. Memory Read Switching Characteristics
PARAMETER
For accesses not immediately following a
HOLD operation
For read accesses immediately following a
HOLD operation
MIN
–1
–1
–1
0
MAX
4
6
4
4
UNIT
ns
ns
ns
ns
td(CLKL-A)
Delay time CLKOUT low to address valid†
time,
td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low
td(CLKL-MSH) Delay time, CLKOUT low to MSTRB high
† Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
64
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
