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TMS320VC5407PGER 参数 Datasheet PDF下载

TMS320VC5407PGER图片预览
型号: TMS320VC5407PGER
PDF下载: 下载PDF文件 查看货源
内容描述: [IC,DSP,16-BIT,QFP,144PIN,PLASTIC]
分类和应用:
文件页数/大小: 107 页 / 1364 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications
5.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
DVDD = 3 V to 3.6 V, IOH = MAX
DVDD = 2.7 V to 3 V, IOH = MAX
IOL = MAX
DVDD = MAX VO = DVSS to DVDD
MAX,
–275
275
–40
With internal pulldown
With internal pulldown, RS = 0
With internal pullups
Bus holders enabled, DVDD = MAX
k
CVDD = 1.5 V, fx = 120 MHz,¶ TC = 25°C
DVDD = 3.0 V, fx = 120 MHz,¶ TC = 25°C
IDLE2
IDLE3
PLL
×
1 mode,
20 MHz input
Divide-by-two mode, CLKIN stopped
–10
–10
–400
–275
–5
60#
20||
2
1
h
5
5
MIN
2.4
2.2
0.4
275
40
800
400
10
275
5
mA
mA
mA
mA
pF
pF
µA
V
V
µA
µA
TYP†
MAX
UNIT
High-level
High level output voltage‡
Low-level output voltage‡
In ut
Input current in high
impedance
A[22:0]
X2/CLKIN
TRST
HPIENA
TMS, TCK, TDI, HPI§
D[15:0], HD[7:0]
All other input-only pins
VOH
VOL
IIZ
II
In ut
Input current
(VI = DVSS to DVDD)
IDDC
IDDP
IDD
Ci
Co
Supply current, core CPU
Supply current, pins
Su ly
Supply current,
standby
Input capacitance
Output capacitance
† All values are typical unless otherwise specified.
‡ All input and output voltage levels except RS, INT0 – INT3, NMI, X2/CLKIN, CLKMD1 – CLKMD3 are LVTTL-compatible.
§ HPI input signals except for HPIENA.
¶ Clock mode: PLL
×
1 with external source
# This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
|| This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the
Calculation of TMS320LC54x Power Dissipation
application report (literature number SPRA164).
k
VIL(MIN)
VI
VIL(MAX) or VIH(MIN)
VI
VIH(MAX)
h
Material with high IDD has been observed with an IDD as high as 7 mA during high temperature testing.
IOL
50
Tester Pin
Electronics
VLoad
C
T
Output
Under
Test
IOH
Where:
IOL
IOH
VLoad
CT
=
=
=
=
1.5 mA (all outputs)
300
µA
(all outputs)
1.5 V
20-pF typical load circuit capacitance
Figure 5–1. 3.3-V Test Load Circuit
November 2001 – Revised July 2003
SPRS007B
59