Electrical Specifications
5.8.2 Memory Write
Table 5–10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
c(CO)
(see
Figure 5–7).
Table 5–10. Memory Write Switching Characteristics
PARAMETER
For accesses not immediately following a
HOLD operation
For read accesses immediately following a
HOLD operation
For accesses not immediately following a
HOLD operation
For read accesses immediately following a
HOLD operation
MIN
–1
–1
2H – 3
2H – 5
–1
2H – 5
2H – 5
–1
2H – 2
0
4
5
2H + 6
2H + 6
4
MAX
4
6
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-A)
Delay time, CLKOUT low to address
valid†
tsu(A)MSL
Setup time, address valid before MSTRB
Setu
low†
td(CLKL-D)W
tsu(D)MSH
th(D)MSH
td(CLKL-MSL)
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
tw(SL)MS
Pulse duration, MSTRB low
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
† Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
November 2001 – Revised July 2003
SPRS007B
67
TI [ TEXAS INSTRUMENTS ]
