Electrical Specifications
Table 5–5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
PARAMETER
tc(CO)
td(CIH-CO)
tf(CO)
tr(CO)
Cycle time, CLKOUT
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
MIN
8.33†
4
TYP
7
1
1
MAX
‡
11
UNIT
ns
ns
ns
ns
tw(COL)
Pulse duration, CLKOUT low
H–3
H
H+3
ns
tw(COH)
Pulse duration, CLKOUT high
H–3
H
H+3
ns
† It is recommended that the PLL clocking option be used for maximum frequency operation.
‡ This device utilizes a fully static design and therefore can operate with tc(CI) approaching
∞.
The device is characterized at frequencies
approaching 0 Hz.
tw(CIH)
tc(CI)
X2/CLKIN
tr(CI)
tw(CIL)
tf(CI)
tc(CO)
td(CIH-CO)
CLKOUT
tf(CO)
tr(CO)
tw(COH)
tw(COL)
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5–3. External Divide-by-Two Clock Timing
62
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
