Electrical Specifications
5.4
Package Thermal Resistance Characteristics
Table 5–1 provides the estimated thermal resistance characteristics for the recommended package types
used on the TMS320VC5407/TMS320VC5404 DSP.
Table 5–1. Thermal Resistance Characteristics
PARAMETER
R
ΘJA
R
ΘJC
GGU
PACKAGE
38
5
PGE
PACKAGE
56
5
UNIT
°C
/ W
°C
/ W
5.5
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
a
c
d
dis
en
f
h
r
su
t
v
w
X
access time
cycle time (period)
delay time
disable time
enable time
fall time
hold time
rise time
setup time
transition time
valid time
pulse duration (width)
Unknown, changing, or don’t care level
Letters and symbols and their meanings:
H
L
V
Z
High
Low
Valid
High impedance
5.6
Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent;
see Section 3.10) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by
the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30
Ω
maximum and power dissipation of 1 mW. The connection of the required circuit, consisting
of the crystal and two load capacitors, is shown in Figure 5–2. The load capacitors, C
1
and C
2
, should be
chosen such that the equation below is satisfied. C
L
(recommended value of 10 pF) in the equation is the load
specified for the crystal.
C
L
+
C
1
C
2
(C
1
)
C
2
)
Table 5–2. Input Clock Frequency Characteristics
MIN
10†
MAX
20‡
UNIT
fx
Input clock frequency
MHz
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching
∞.
The device is characterized at frequencies
approaching 0 Hz
‡ It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
60
SPRS007B
November 2001 – Revised July 2003
TI [ TEXAS INSTRUMENTS ]
