Electrical Specifications
X1
Crystal
X2/CLKIN
C1
C2
Figure 5–2. Internal Divide-by-Two Clock Option With External Crystal
5.7
Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.7.1 Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
to generate the internal machine cycle. The selection of the clock mode is described in Section 3.10.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5–4.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 5–3 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5–3. Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options
CLKMD1
0
1
1
CLKMD2
0
0
1
CLKMD3
0
1
1
CLOCK MODE
1/2, PLL and oscillator disabled
1/4, PLL and oscillator disabled
1/2, PLL and oscillator disabled
Table 5–4 and Table 5–5 assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Figure 5–3).
Table 5–4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
MIN
tc(CI)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
20
4
4
MAX
UNIT
ns
ns
ns
ns
ns
November 2001 – Revised July 2003
SPRS007B
61
TI [ TEXAS INSTRUMENTS ]
