TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
9.9.3.1.2 SPI Master Mode External Timing (Clock Phase = 1)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
UNIT
(5)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M
0.5tc(LSPCLK) –10
0.5tc(SPC)M
0.5tc(LSPCLK) –10
0.5tc(SPC)M
0.5tc(LSPCLK) –10
0.5tc(SPC)M
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
–
0.5tc(SPC)M
–
2
3
6
tw(SPC1)M
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
+
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
tw(SPC2)M
ns
ns
0.5tc(SPC)M –10
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
+
Delay time, SPISIMO valid to
SPICLK
td(SIMO)M
Valid time, SPISIMO valid after
SPICLK
–
7
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
ns
ns
ns
ns
0.5tc(SPC)M –10
0.5tc(LSPCLK) –10
Setup time, SPISOMI before
SPICLK
10
11
23
26
0
26
Hold time, SPISOMI valid after
SPICLK
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) –10
3tc(SYSCLK) –10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
0.5tc(LSPCLK) –10
–
24
td(STE)M
ns
0.5tc(SPC) –10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
图9-30. SPI Master Mode External Timing (Clock Phase = 1)
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