TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.9.3.1 SPI 主模式电气数据/时序
节9.9.3.1.1 列出了主模式时序（时钟相位= 0），节9.9.3.1.2 列出了主模式时序（时钟相位= 1）。图9-29 和图
9-30 显示了时序波形。
9.9.3.1.1 SPI Master Mode External Timing (Clock Phase = 0)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
UNIT
(5)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
0.5tc(SPC)M + 0.5tc(LSPCLK)
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M
+
2
tw(SPC1)M
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
–10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
–
0.5tc(SPC)M
–
3
4
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
ns
ns
ns
ns
ns
ns
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
0.5tc(LSPCLK) –10
Delay time, SPICLK to
SPISIMO valid
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M –
0.5tc(LSPCLK) –10
5
0.5tc(SPC)M –10
Setup time, SPISOMI before
SPICLK
8
26
0
26
Hold time, SPISOMI valid after
SPICLK
9
0
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M
–
23
3tc(SYSCLK) –10
3tc(SYSCLK) –10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M
0.5tc(LSPCLK) –10
–
24
td(STE)M
ns
0.5tc(SPC)M –10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
图9-29. SPI Master Mode External Timing (Clock Phase = 0)
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