TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
9.9.4 Serial Communications Interface (SCI) Module
The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
备注
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
LSPCLK
Baud rate =
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
16
Baud rate =
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– One or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (nonreturn-to-zero) format
备注
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is
read as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 4-level transmit/receive FIFO
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
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