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TMS320F28026FPTT 参数 Datasheet PDF下载

TMS320F28026FPTT图片预览
型号: TMS320F28026FPTT
PDF下载: 下载PDF文件 查看货源
内容描述: [具有 60MHz 频率、32KB 闪存、InstaSPIN-FOC 的 C2000™ 32 位 MCU | PT | 48 | -40 to 105]
分类和应用: 时钟微控制器外围集成电路装置闪存
文件页数/大小: 140 页 / 4683 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026  
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023  
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200  
ZHCSA13P NOVEMBER 2008 REVISED FEBRUARY 2021  
www.ti.com.cn  
9.9.3.2 SPI 从模式电气数据/时序  
9.9.3.2.1 列出了从模式时序时钟相= 0),9.9.3.2.2 列出了从模式时序时钟相= 19-31 图  
9-32 显示了时序波形。  
9.9.3.2.1 SPI Slave Mode External Timing (Clock Phase = 0)  
NO.  
(1) (2)  
PARAMETER  
MIN  
MAX UNIT  
(4) (3)  
(5)  
12 tc(SPC)S  
13 tw(SPC1)S  
14 tw(SPC2)S  
15 td(SOMI)S  
16 tv(SOMI)S  
19 tsu(SIMO)S  
20 th(SIMO)S  
25 tsu(STE)S  
26 th(STE)S  
Cycle time, SPICLK  
4tc(SYSCLK)  
2tc(SYSCLK) 1  
2tc(SYSCLK) 1  
ns  
ns  
ns  
Pulse duration, SPICLK first pulse  
Pulse duration, SPICLK second pulse  
Delay time, SPICLK to SPISOMI valid  
Valid time, SPISOMI data valid after SPICLK  
Setup time, SPISIMO valid before SPICLK  
Hold time, SPISIMO data valid after SPICLK  
Setup time, SPISTE active before SPICLK  
Hold time, SPISTE inactive after SPICLK  
21  
ns  
ns  
ns  
ns  
ns  
ns  
0
1.5tc(SYSCLK)  
1.5tc(SYSCLK)  
1.5tc(SYSCLK)  
1.5tc(SYSCLK)  
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.  
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)  
(3) tc(LCO) = LSPCLK cycle time  
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:  
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX  
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.  
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).  
12  
SPICLK  
(clock polarity = 0)  
13  
14  
SPICLK  
(clock polarity = 1)  
15  
16  
SPISOMI  
SPISOMI Data Is Valid  
19  
20  
SPISIMO Data  
Must Be Valid  
SPISIMO  
SPISTE  
25  
26  
9-31. SPI Slave Mode External Timing (Clock Phase = 0)  
Copyright © 2022 Texas Instruments Incorporated  
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1  
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-  
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200  
 
 
 
 
 
 
 
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