TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-38. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master
Mode(1) (see Figure 6-22)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
9.5
18
20
22
td(PCLK-HDV)
Delay time, PCLK edge to HD valid
Delay time, PCLK edge to VD valid
Delay time, PCLK edge to C_FIELD valid
2
2
2
ns
ns
ns
td(PCLK-VDV)
9.5
td(PCLK-C_FIELDV)
9.5
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
17
18
HD
19
20
VD
21
22
C_WE/C_FIELD
Figure 6-22. VPFE (CCD) Master Mode Control Output Data Timing
224
Peripheral Information and Electrical Specifications
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