TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
8, 10
7, 9
HD/VD
11, 13
12, 14
C_WE/C_FIELD
CCD[15:0]
5
6
Figure 6-20. VPFE (CCD) Slave Mode Input Data Timing
Table 6-37. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 6-21)
-400
-500
-600
NO.
UNIT
MIN
MAX
15
16
23
24
tsu(CCDV-PCLK)
th(PCLK-CCDV)
tsu(CWEV-PCLK)
th(PCLK-CWEV)
Setup time, CCD valid before PCLK edge
Hold time, CCD valid after PCLK edge
Setup time, C_WE valid before PCLK edge
Hold time, C_WE valid after PCLK edge
4.5
0.5
4.5
0.5
ns
ns
ns
ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
(Positive Edge Clocking)
PCLK
(Positive Edge Clocking)
15
16
CCD[15:0]
23
24
C_WE/C_FIELD
Figure 6-21. VPFE (CCD) Master Mode Input Data Timing
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