TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-40. OSD Register Descriptions (continued)
0x01C7 26F4
0x01C7 26F8
0x01C7 26FC
TRANSPVAL
RSV6
CLUT RAM Setup
Reserved
PPVWIN0ADR
Ping-Pong Video Window 0 Address
6.10.2.2 Video Encoder (VENC)
Analog/DACs interface of the Video Encoder (VENC) supports the following features.
•
•
Master Clock Input - 27MHz (x2 Upsampling)
SDTV Support
–
–
–
–
–
–
–
–
–
Composite NTSC-M, PAL-B/D/G/H/I
S-Video (Y/C)
Component YPbPr (SMPTE/EBU N10, Betacam, MII)
RGB
Non-Interlace
CGMS/WSS
Line 21 Closed Caption Data Encoding
Chroma Low Pass Filter 1.5MHz/3MHz
Programmable SC-H phase
•
HDTV Support
–
–
–
–
Progressive Output (525p/625p)
Component YPbPr
RGB
CGMS/WSS
•
•
•
•
•
•
4 10-bit Over-Sampling D/A Converters
Optional 7.5% Pedestal
16-235/0-255 Input Amplitude Selectable
Programmable Luma Delay
Master/Slave Operation
Internal Color Bar Generation (100%/75%)
The Digital LCD Controller (DLCD) of the VENC supports the following features.
•
•
Programmable DCLK
Various Output Formats
–
–
–
–
YCbCr 16bit
YCbCr 8bit
ITU-R BT. 656
Parallel RGB 24bit
•
•
•
•
Low Pass Filter for Digital RGB Output
Programmable Timing Generator
Master/Slave Operation
Internal Color Bar Generation (100%/75%)
The VENC register memory mapping including the Digital LCD and DACs is shown in Table 6-41.
Table 6-41. VENC (Including Digital LCD and DACs) Register Descriptions
Address
Register
Description
0x01C7 2400
0x01C7 2404
VMOD
Video Mode
VIDCTL
Video Interface I/O Control
228
Peripheral Information and Electrical Specifications
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