TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-3. PLLC1 Programming for CLKDIV1, CLKDIV3, CLKDIV6 Domains
CLKDIV1 DOMAIN
(SYSCLK1)
CLKDIV3 DOMAIN
(SYSCLK2)
CLKDIV6 DOMAIN
(SYSCLK3)
PLL1
Divide-Down
PLL1
Divide-Down
PLL1
Divide-Down
PLLDIV1.RATIO
PLLDIV2.RATIO
PLLDIV3.RATIO
DIV1
DIV2
DIV3
/1
/2
/3
0
1
2
/3
/6
/9
2
5
8
/6
5
/12
/18
11
17
HECC
UARTs (x2)
I2C
AUXCLK
MXI/CLKIN
(27 MHz)
PWMs (x3)
Timers (x3)
OBSCLK
(CLKOUT0 Pin)
OSCDIV1 (/1)
PLLDIV1 (/1)
PLLDIV3 (/6)
PLLDIV2 (/3)
SYSCLK1
DSP Subsystem
SYSCLK3
SYSCLK2
HPI
SCR
EDMA
PCI
VLYNQ
EMAC
BPDIV (/1)
PLL Controller 1
EMIFA
McASP0
McBSP0
McBSP1
GPIO
VPFE
VPBE
PCLK
VPBECLK
DACs
PLLDIV2 (/10)
PLLDIV1 (/2)
DDR2 PHY
DDR2 VTP
BPDIV
DDR2 Mem Ctlr
PLL Controller 2
Figure 6-4. PLL1 and PLL2 Clock Domain Block Diagram
For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-5 and Figure 6-6,
respectively.
170
Peripheral Information and Electrical Specifications
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