TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-1. DM6437 Power and Clock Domains
Power Domain
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Clock Domain
CLKIN
Peripheral/Module
UART0
UART1
HECC
CLKIN
CLKIN
CLKIN
I2C
CLKIN
Timer0
Timer1
Timer2
PWM0
PWM1
PWM2
DDR2
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV1
VPSS
EDMA
PCI
SCR
GPSC
LPSCs
PLLC1
PLLC2
Ice Pick
EMIFA
HPI
VLYNQ
EMAC
McASP0
McBSP0
McBSP1
GPIO
C64x+ CPU
Table 6-2. DM6437 Clock Domains
DOMAIN CLOCK
SOURCE
FIXED RATIO vs.
SYSCLK1 FREQUENCY
EXAMPLE
FREQUENCY (MHz)
SUBSYSTEM
CLOCK DOMAIN
Peripherals (CLKIN Domain)
DSP Subsystem
CLKIN
PLLC1 AUXCLK(1)
PLLC1 SYSCLK1
PLLC1 SYSCLK2
PLLC1 SYSCLK2
PLLC1 SYSCLK2
PLLC1 SYSCLK3
–
27 MHz
594 MHz
198 MHz
198 MHz
198 MHz
99 MHz
CLKDIV1
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV6
1:1
1:3
1:3
1:3
1:6
EDMA3
VPSS
Peripherals (CLKDIV3 Domain)
Peripherals (CLKDIV6 Domain)
(1) PLLC1 AUXCLK runs at exactly the same frequency as the device clock source from the MXI/CLKIN pin.
The CLKDIV1:CLKDIV3:CLKDIV6 ratio must be strictly followed by programming the PLL Controller 1
(PLLC1) PLLDIV1, PLLDIV2, and PLLDIV3 registers appropriately (see Table 6-3).
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Peripheral Information and Electrical Specifications
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