TMS320DM6437
Digital Media Processor
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SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
As with the selection of any component, verification of capacitor availability over the product's production
lifetime should be considered.
For more details on capacitor usage and placement, see the Implementing DDR2 PCB Layout on the
TMS320DM643x DMP Application Report (literature number SPRAATBD).
6.3.4 DM6437 Power and Clock Domains
The DM6437 includes one single power domain — the "Always On" power domain. The "Always On"
power domain is always on when the chip is on. The "Always On" domain is powered by the CVDD pins of
the DM6437. All DM6437 modules lie within the "Always On" power domain. Table 6-1 provides a listing of
the DM6437 clock domains.
One primary reference clock is required for the DM6437 device. It can be either a crystal input or driven by
external oscillators. A 27-MHz crystal is recommended for the PLLs, which generate the internal clocks for
the digital media processor (DMP), peripherals, and EDMA3.
The DM6437 architecture is divided into the power and clock domains shown in Table 6-1. Table 6-2 and
Table 6-3 further discuss the clock domains and their ratios. Figure 6-4 shows the Clock Domain block
diagram.
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Peripheral Information and Electrical Specifications
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