TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-18
Ethernet Boot Mode Parameter Table (Part 2 of 2)
Byte
Offset
Configured Through Boot
Configuration Pins
Name
Description
58
60
PKT PLL Cfg MSW
PKT PLL CFG LSW
The packet subsystem PLL configuration, MSW
The packet subsystem PLL configuration, LSW
-
-
End of Table 2-18
2.5.3.4 PCIe Boot Parameter Table
Table 2-19
PCIe Boot Mode Parameter Table
Byte
Offset
Configured Through Boot
Configuration Pins
Name
Description
12
Options
-
Bit 0 Mode
0 = Host Mode (Direct boot mode)
1 = Boot Table Boot Mode
Bit 1 Configuration of PCIe
0 = PCIe is configured by RBL
1 = PCIe is not configured by RBL
Bits 3-2 Reserved
Bit 4 Multiplier
0 = SERDES PLL configuration is done based on SERDES register values
1 = SERDES PLL configuration based on the reference clock values
Bits 15-5 Reserved
14
16
18
Address Width
Link Rate
PCI address width, can be 32 or 64
SerDes frequency, in Mbps. Can be 2500 or 5000
-
-
-
Reference clock
Reference clock frequency, in units of 10 kHz. Value values are 10000
(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz), and 31250
(312.5 MHz). A value of 0 means that value is already in the SerDes
configuration parameters and will not be computed by the boot ROM.
20
22
24
26
28
30
32
34
36
38
40
42
44
46
Window 1 Size
Window 1 size.
YES
Window 2 Size
Window 2 size.
YES
Window 3 Size
Window 3 size. Valid only if address width is 32.
Window 4 Size. Valid only if the address width is 32.
Vendor ID
YES
Window 4 Size
YES
Vendor ID
-
-
-
-
-
-
-
-
-
-
Device ID
Device ID
Class code Rev ID MSW
Class code Rev ID LSW
SerDes Cfg MSW
SerDes Cfg LSW
Class code revision ID MSW
Class code revision ID LSW
PCIe SerDes config word, MSW
PCIe SerDes config word, LSW
SerDes lane config word, MSW, lane 0
SerDes lane config word, LSW, lane 0
SerDes lane config word, MSW, lane 1
SerDes lane config word, LSW, lane 1
SerDes lane 0 Cfg MSW
SerDes lane 0 Cfg LSW
SerDes lane 1 Cfg MSW
SerDes lane 1 Cfg LSW
End of Table 2-19
Copyright 2013 Texas Instruments Incorporated
Device Overview 37
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