TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.5.2.7 HyperLink Boot Device Configuration
Figure 2-10
HyperLink Boot Device Configuration Fields
9
8
7
6
5
4
3
Reserved
Data Rate
Ref Clock
Reserved
Table 2-14
HyperLink Boot Device Configuration Field Descriptions
Bit
9
Field
Description
Reserved
Reserved
8-7
Data Rate
Ref Clocks
Reserved
HyperLink data rate configuration
0 = 1.25 GBaud
1 = 3.125 GBaud
2 = 6.25 GBaud
3 = Reserved
6-5
HyperLink reference clock configuration
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved
4-3
Reserved
End of Table 2-14
2.5.3 Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is the
most common format the RBL employs to determine the boot flow. These boot parameter tables have certain
parameters common across all the boot modes, while the rest of the parameters are unique to the boot modes. The
common entries in the boot parameter table are shown in the table below:
Table 2-15
Boot Parameter Table Common Parameters
Byte
Offset
Name
Description
0
2
Length
The length of the table, including the length field, in bytes.
Checksum
The 16 bits ones complement of the ones complement of the entire table. A value of 0 will disable checksum verification
of the table by the boot ROM.
4
Boot Mode
Port Num
Internal values used by RBL for different boot modes.
Identifies the device port number to boot from, if applicable
PLL configuration, MSW
6
8
SW PLL, MSW
SW PLL, LSW
10
PLL configuration, LSW
End of Table 2-15
2.5.3.1 EMIF16 Boot Parameter Table
Table 2-16
Byte
EMIF16 Boot Mode Parameter Table
Configured Through Boot
Configuration Pins
Offset
Name
Description
12
Options
Option for EMIF16 boot (currently none)
-
-
-
-
14
Type
Only boot from NOR flash is supported for C6678
Most significant bit for Branch address (depends on chip select)
Least significant bit for Branch address (depends on chip select)
16
Branch Address MSW
Branch Address LSW
18
34
Device Overview
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