TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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2.5.3.7 HyperLink Boot Parameter Table
Table 2-22
HyperLink Boot Mode Parameter Table
Configured Through Boot
Configuration Pins
Byte Offset Name
Description
12
Options
Bit 0 Mode
-
0 = Host Mode (Direct boot mode)
1 = Boot Table Boot Mode
Bit 1 Configuration of PCIe
0 = PCIe is configured by RBL
1 = PCIe is not configured by RBL
Bits 15-2 Reserved
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Number of Lanes
SerDes cfg msw
SerDes cfg lsw
Number of Lanes to be configured
HyperLink SerDes config word, MSW
HyperLink SerDes config word, LSW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SerDes CFG RX lane 0 cfg msw SerDes RX lane config word, msw lane 0
SerDes CFG RXlane 0 cfg lsw
SerDes CFG TX lane 0 cfg msw
SerDes CFG TXlane 0 cfg lsw
SerDes RX lane config word, lsw, lane 0
SerDes TX lane config word, msw lane 0
SerDes TX lane config word, lsw, lane 0
SerDes CFG RX lane 1 cfg msw SerDes RX lane config word, msw lane 1
SerDes CFG RXlane 1 cfg lsw
SerDes CFG TX lane 1 cfg msw
SerDes CFG TXlane 1 cfg lsw
SerDes RX lane config word, lsw, lane 1
SerDes TX lane config word, msw lane 1
SerDes TX lane config word, lsw, lane 1
SerDes CFG RX lane 2 cfg msw SerDes RX lane config word, msw lane 2
SerDes CFG RXlane 2 cfg lsw
SerDes CFG TX lane 2 cfg msw
SerDes CFG TXlane 2 cfg lsw
SerDes RX lane config word, lsw, lane 2
SerDes TX lane config word, msw lane 2
SerDes TX lane config word, lsw, lane 2
SerDes CFG RX lane 3 cfg msw SerDes RX lane config word, msw lane 3
SerDes CFG RXlane 3 cfg lsw
SerDes CFG TX lane 3 cfg msw
SerDes CFG TXlane 3 cfg lsw
SerDes RX lane config word, lsw, lane 3
SerDes TX lane config word, msw lane 3
SerDes TX lane config word, lsw, lane 3
End of Table 2-22
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Device Overview 39
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