TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-47
LRESET and NMI Decoding (Part 2 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
0001
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Assert NMI to CorePac1
Assert NMI to CorePac2
Assert NMI to CorePac3
Assert NMI to CorePac4
Assert NMI to CorePac5
Assert NMI to CorePac6
Assert NMI to CorePac7
Assert NMI to all CorePacs
0010
0011
0100
0101
0110
0111
1xxx
End of Table 7-47
7.9.5 External Interrupts Electrical Data/Timing
Table 7-48
(see Figure 7-30)
NMI and Local Reset Timing Requirements (1)
No.
Min
12*P
12*P
12*P
12*P
12*P
12*P
12*P
Max Unit
1
1
1
2
2
2
3
tsu(LRESET-LRESETNMIENL)
Setup Time - LRESET valid before LRESETNMIEN low
Setup Time - NMI valid before LRESETNMIEN low
Setup Time - CORESEL[2:0] valid before LRESETNMIEN low
Hold Time - LRESET valid after LRESETNMIEN high
Hold Time - NMI valid after LRESETNMIEN high
Hold Time - CORESEL[2:0] valid after LRESETNMIEN high
Pulse Width - LRESETNMIEN low width
ns
ns
ns
ns
ns
ns
ns
tsu(NMI-LRESETNMIENL)
tsu(CORESELn-LRESETNMIENL)
th(LRESETNMIENL-LRESET)
th(LRESETNMIENL-NMI)
th(LRESETNMIENL-CORESELn)
tw(LRESETNMIEN)
End of Table 7-48
1 P = 1/SYSCLK1 frequency in ns.
Figure 7-30
NMI and Local Reset Timing
1
2
CORESEL[3:0]/
LRESET/
NMI
3
LRESETNMIEN
7.9.6 Host Interrupt Output
The C66x CorePac can assert an event to the external host processor using HOUT. Table 7-49 provides the timing
for the HOUT pulse. For more details, see section 3.3.15 .
188
Peripheral Information and Electrical Specifications
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