TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-52
Privilege ID Settings (Part 2 of 2)
Privilege ID Master
Privilege Level
Security Level
Access Type
10
QM_SS Packet
DMA/QM_SS Second
User
Non-secure
DMA
11
12
13
14
15
PCIe
Driven by PCIe module
Driven by Debug_SS
Driven by HyperLink
Supervisor
Non-secure
DMA
Debug_SS
HyperLink
HyperLink
TSIP0/1
Driven by Debug_SS DMA
Non-secure
Non-secure
Non-secure
DMA
DMA
DMA
User
End of Table 7-52
Table 7-53 shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to determine
allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters,
master IDs are unique to each master.
Table 7-53
Master ID Settings (Part 1 of 2) (1)
Master ID
Master
0
CorePac0
1
CorePac1
2
CorePac2
3
CorePac3
4
CorePac4
5
CorePac5
6
CorePac6
7
CorePac7
8
CorePac0_CFG
CorePac1_CFG
CorePac2_CFG
CorePac3_CFG
CorePac4_CFG
CorePac5_CFG
CorePac6_CFG
CorePac7_CFG
EDMA0_TC0 read
EDMA0_TC0 write
EDMA0_TC1 read
EDMA0_TC1 write
EDMA1_TC0 read
EDMA1_TC0 write
EDMA1_TC1 read
EDMA1_TC1 write
EDMA1_TC2 read
EDMA1_TC2 write
EDMA1_TC3 read
EDMA1_TC3 write
EDMA2_TC0 read
EDMA2_TC0 write
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 191
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