TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-53
Master ID Settings (Part 2 of 2) (1)
Master ID
Master
30
EDMA2_TC1 read
EDMA2_TC1 write
EDMA2_TC2 read
EDMA2_TC2 write
EDMA2_TC3 read
EDMA2_TC3 write
Reserved
31
32
33
34
35
36 - 37
38 - 39
40 - 47
48
SRIO Packet DMA
Reserved
Debug SS
49
EDMA3CC0
50
EDMA3CC1
51
EDMA3CC2
52
MSMC (2)
53
PCIe
54
SRIO_Master
55
HyperLink
56 - 59
60 - 85
86
Network Coprocessor Packet DMA
Reserved
TSIP0
87
TSIP1
88 - 91
92 - 93
94 - 127
128
Queue Manager Packet DMA
Queue Manager Second
Reserved
Tracer_core_0 (3)
Tracer_core_1
Tracer_core_2
Tracer_core_3
Tracer_core_4
Tracer_core_5
Tracer_core_6
Tracer_core_7
Tracer_MSMC0
Tracer_MSMC1
Tracer_MSMC2
Tracer_MSMC3
Tracer_DDR
129
130
131
132
133
134
135
136
137
138
139
140
141
Tracer_SM
142
Tracer_QM_CFG
Tracer_QM_DMA
Tracer_CFG
143
144
End of Table 7-53
1 Some of the Packet DMA-based peripherals require multiple master IDs. Queue Manager Packet DMA is assigned with 88,89,90,91, but only 88-89 are actually used. For
Network Coprocessor Packet DMA port, 56,57,58,59 are assigned while only 1 (56) is actually used. There are two master ID values are assigned for the Queue Manager
Second master port, one master ID for external linking RAM and the other one for the PDSP/MCDM accesses.
192
Peripheral Information and Electrical Specifications
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