TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-46
IPC Generation Registers (IPCGRx) (Part 2 of 2)
Address Start
0x02620258
0x0262025C
0x02620260
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202BC
End of Table 7-46
Address End
0x0262025B
0x0262025F
0x0262027B
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202BB
0x026202BF
Size
4B
Register Name
IPCGR6
Description
IPC Generation Register for CorePac6
IPC Generation Register for CorePac7
Reserved
4B
IPCGR7
28B
4B
Reserved
IPCGRH
IPCAR0
IPC Generation Register for Host
4B
IPC Acknowledgement Register for CorePac0
IPC Acknowledgement Register for CorePac1
IPC Acknowledgement Register for CorePac2
IPC Acknowledgement Register for CorePac3
IPC Acknowledgement Register for CorePac4
IPC Acknowledgement Register for CorePac5
IPC Acknowledgement Register for CorePac6
IPC Acknowledgement Register for CorePac7
Reserved
4B
IPCAR1
4B
IPCAR2
4B
IPCAR3
4B
IPCAR4
4B
IPCAR5
4B
IPCAR6
4B
IPCAR7
28B
4B
Reserved
IPCARH
IPC Acknowledgement Register for Host
7.9.4 NMI and LRESET
Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One
NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured
to select between the CorePacs available as shown in Table 7-47.
Table 7-47
LRESET and NMI Decoding (Part 1 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
XXXX
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
0000
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No local reset or NMI assertion.
Assert local reset to CorePac0
Assert local reset to CorePac1
Assert local reset to CorePac2
Assert local reset to CorePac3
Assert local reset to CorePac4
Assert local reset to CorePac5
Assert local reset to CorePac6
Assert local reset to CorePac7
Assert local reset to all CorePacs
De-assert local reset & NMI to CorePac0
De-assert local reset & NMI to CorePac1
De-assert local reset & NMI to CorePac2
De-assert local reset & NMI to CorePac3
De-assert local reset & NMI to CorePac4
De-assert local reset & NMI to CorePac5
De-assert local reset & NMI to CorePac6
De-assert local reset & NMI to CorePac7
De-assert local reset & NMI to all CorePacs
Assert NMI to CorePac0
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 187
TI [ TEXAS INSTRUMENTS ]
