TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-44
CIC2 Register
Address Offset
0x498
Register Mnemonic
Register Name
CH_MAP_REG38
CH_MAP_REG39
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
HINT_MAP_REG10
HINT_MAP_REG11
HINT_MAP_REG12
ENABLE_HINT_REG0
ENABLE_HINT_REG1
Interrupt Channel Map Register for 152 to 152+3
Interrupt Channel Map Register for 156 to 156+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Interrupt Map Register for 40 to 40+3
Host Interrupt Map Register for 44 to 44+3
Host Interrupt Map Register for 48 to 48+3
Host Int Enable Register 0
0x49c
0x800
0x804
0x808
0x80c
0x810
0x814
0x818
0x81c
0x820
0x824
0x828
0x82c
0x830
0x1500
0x1504
End of Table 7-44
Host Int Enable Register 1
7.9.2.3 CIC3 Register Map
Table 7-45
CIC3 Register
Address Offset
0x0
Register Mnemonic
Register Name
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
ENA_STATUS_REG0
ENA_STATUS_REG1
ENABLE_REG0
Global Host Int Enable Register
Status Set Index Register
0x20
0x24
Status Clear Index Register
Enable Set Index Register
0x28
0x2c
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
0x34
0x38
0x200
0x204
0x280
0x284
0x300
0x304
0x380
0x384
0x400
0x404
0x408
0x40c
0x410
Raw Status Register 1
Enabled Status Register 0
Enabled Status Register 1
Enable Register 0
ENABLE_REG1
Enable Register 1
ENABLE_CLR_REG0
ENABLE_CLR_REG1
CH_MAP_REG0
Enable Clear Register 0
Enable Clear Register 1
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
Interrupt Channel Map Register for 8 to 8+3
Interrupt Channel Map Register for 12 to 12+3
Interrupt Channel Map Register for 16 to 16+3
CH_MAP_REG1
CH_MAP_REG2
CH_MAP_REG3
CH_MAP_REG4
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 185
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