TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-39
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 5)
Input Event# on CIC
System Interrupt
EDMA3CC2 CCINT7
EDMA3CC0 CC_ERRINT
EDMA3CC0 CC_MPINT
EDMA3CC0 TC_ERRINT0
EDMA3CC0 TC_ERRINT1
EDMA3CC0 CC_GINT
Reserved
Description
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
EDMA3CC2 individual completion interrupt
EDMA3CC0 error interrupt
EDMA3CC0 memory protection interrupt
EDMA3CC0 TC0 error interrupt
EDMA3CC0 TC1 error interrupt
EDMA3CC0 GINT
EDMA3CC0 CCINT0
EDMA3CC0 CCINT1
EDMA3CC0 CCINT2
EDMA3CC0 CCINT3
EDMA3CC0 CCINT4
EDMA3CC0 CCINT5
EDMA3CC0 CCINT6
EDMA3CC0 CCINT7
Reserved
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
QM_INT_PASS_TXQ_PEND_12
PCIEXpress_ERR_INT
PCIEXpress_PM_INT
PCIEXpress_Legacy_INTA
PCIEXpress_Legacy_INTB
PCIEXpress_Legacy_INTC
PCIEXpress_Legacy_INTD
SPIINT0
Queue manager pend event
Protocol error interrupt
Power management interrupt
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
SPI interrupt0
SPIINT1
SPI interrupt1
SPIXEVT
Transmit event
SPIREVT
Receive event
I2C interrupt
I2C receive event
I2C transmit event
I2CINT
I2CREVT
I2CXEVT
Reserved
Reserved
TETBHFULLINT
TETB is half full
TETBFULLINT
TETB is full
TETBACQINT
Acquisition has been completed
Overflow condition occur
TETBOVFLINT
TETBUNFLINT
Underflow condition occur
MDIO_LINK_INTR0
MDIO_LINK_INTR1
MDIO_USER_INTR0
MDIO_USER_INTR1
MISC_INTR
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MISC interrupt
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
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Peripheral Information and Electrical Specifications 169
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