TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-38 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
Table 7-38
TMS320C6678 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)
Event Number
Interrupt Event
EVT0
Description
0
1
2
3
4
5
6
7
8
9
Event combiner 0 output
Event combiner 1 output
Event combiner 2 output
Event combiner 3 output
TETB is half full
EVT1
EVT2
EVT3
TETBHFULLINTn (1)
(1)
TETBFULLINTn
TETB is full
TETBACQINTn (1)
TETBOVFLINTn (1)
TETBUNFLINTn (1)
EMU_DTDMA
Acquisition has been completed
Overflow condition interrupt
Underflow condition interrupt
ECM interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
MSMC_mpf_errorn (2)
Memory protection fault indicators for local core
RTDX receive complete
EMU_RTDXRX
EMU_RTDXTX
RTDX transmit complete
IDMA0
IDMA channel 0 interrupt
IDMA1
SEMERRn (3)
SEMINTn (3)
PCIExpress_MSI_INTn (4)
TSIP0_ERRINT[n] (5)
TSIP1_ERRINT[n] (5)
INTDST(n+16) (6)
CIC0_OUT(32+0+11*n) (7) Or CIC1_OUT(32+0+11*(n-4)) (7)
CIC0_OUT(32+1+11*n) (7) Or CIC1_OUT(32+1+11*(n-4)) (7)
CIC0_OUT(32+2+11*n) (7) Or CIC1_OUT(32+2+11*(n-4)) (7)
CIC0_OUT(32+3+11*n) (7) Or CIC1_OUT(32+3+11*(n-4)) (7)
CIC0_OUT(32+4+11*n) (7) Or CIC1_OUT(32+4+11*(n-4)) (7)
CIC0_OUT(32+5+11*n) (7) Or CIC1_OUT(32+5+11*(n-4)) (7)
CIC0_OUT(32+6+11*n) (7) Or CIC1_OUT(32+6+11*(n-4)) (7)
CIC0_OUT(32+7+11*n) (7) Or CIC1_OUT(32+7+11*(n-4)) (7)
CIC0_OUT(32+8+11*n) (7) Or CIC1_OUT(32+8+11*(n-4)) (7)
CIC0_OUT(32+9+11*n) (7) Or CIC1_OUT(32+9+11*(n-4)) (7)
CIC0_OUT(32+10+11*n) (7) Or CIC1_OUT(32+10+11*(n-4)) (7)
QM_INT_LOW_0
IDMA channel 1 interrupt
Semaphore error interrupt
Semaphore interrupt
Message signaled interrupt mode
TSIP0 receive/transmit error interrupt
TSIP1 receive/transmit error interrupt
SRIO Interrupt
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
QM Interrupt for 0~31 Queues
QM Interrupt for 32~63 Queues
QM Interrupt for 64~95 Queues
QM Interrupt for 96~127 Queues
QM Interrupt for 128~159 Queues
QM Interrupt for 160~191 Queues
QM Interrupt for 192~223 Queues
QM_INT_LOW_1
QM_INT_LOW_2
QM_INT_LOW_3
QM_INT_LOW_4
QM_INT_LOW_5
QM_INT_LOW_6
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 165
TI [ TEXAS INSTRUMENTS ]
