欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320C6678XCYP25 参数 Datasheet PDF下载

TMS320C6678XCYP25图片预览
型号: TMS320C6678XCYP25
PDF下载: 下载PDF文件 查看货源
内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 242 页 / 2088 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320C6678XCYP25的Datasheet PDF文件第167页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第168页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第169页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第170页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第172页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第173页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第174页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第175页  
TMS320C6678  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS691D—April 2013  
www.ti.com  
Table 7-39  
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 4 of 5)  
Input Event# on CIC  
System Interrupt  
INTDST4  
Description  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
RapidIO interrupt  
INTDST5  
RapidIO interrupt  
INTDST6  
RapidIO interrupt  
INTDST7  
RapidIO interrupt  
INTDST8  
RapidIO interrupt  
INTDST9  
RapidIO interrupt  
INTDST10  
INTDST11  
INTDST12  
INTDST13  
INTDST14  
INTDST15  
EASYNCERR  
RapidIO interrupt  
RapidIO interrupt  
RapidIO interrupt  
RapidIO interrupt  
RapidIO interrupt  
RapidIO interrupt  
EMIF16 error interrupt  
TRACER_CORE_4_INTD  
TRACER_CORE_5_INTD  
TRACER_CORE_6_INTD  
TRACER_CORE_7_INTD  
QM_INT_PKTDMA_0  
QM_INT_PKTDMA_1  
RapidIO_INT_PKTDMA_0  
PASS_INT_PKTDMA_0  
SmartReflex_intrreq0  
SmartReflex_intrreq1  
SmartReflex_intrreq2  
SmartReflex_intrreq3  
VPNoSMPSAck  
Tracer sliding time window interrupt for individual core  
Tracer sliding time window interrupt for individual core  
Tracer sliding time window interrupt for individual core  
Tracer sliding time window interrupt for individual core  
Queue manager Interrupt for packet DMA starvation  
Queue manager Interrupt for packet DMA starvation  
RapidIO Interrupt for packet DMA starvation  
Network coprocessor Interrupt for packet DMA starvation  
SmartReflex sensor interrupt  
SmartReflex sensor interrupt  
SmartReflex sensor interrupt  
SmartReflex sensor interrupt  
VPVOLTUPDATE has been asserted but SMPS has not been responded to in a  
defined time interval  
142  
VPEqValue  
SRSINTERUPTZ is asserted, but the new voltage is not different from the  
current SMPS voltage  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
VPMaxVdd  
The new voltage required is equal to or greater than MaxVdd.  
The new voltage required is equal to or less than MinVdd.  
The FSM of Voltage processor is in idle.  
VPMinVdd  
VPINIDLE  
VPOPPChangeDone  
Reserved  
The average frequency error is within the desired limit.  
UARTINT  
UART interrupt  
URXEVT  
UART receive event  
UTXEVT  
UART transmit event  
QM_INT_PASS_TXQ_PEND_17  
QM_INT_PASS_TXQ_PEND_18  
QM_INT_PASS_TXQ_PEND_19  
QM_INT_PASS_TXQ_PEND_20  
QM_INT_PASS_TXQ_PEND_21  
QM_INT_PASS_TXQ_PEND_22  
QM_INT_PASS_TXQ_PEND_23  
Queue manager pend event  
Queue manager pend event  
Queue manager pend event  
Queue manager pend event  
Queue manager pend event  
Queue manager pend event  
Queue manager pend event  
Copyright 2013 Texas Instruments Incorporated  
Peripheral Information and Electrical Specifications 171  
 复制成功!