TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-37
EDMA3CC2 Events for C6678 (Part 2 of 2)
Event Number
Event
Event Description
44
CIC2_OUT24
CIC2_OUT25
CIC2_OUT26
CIC2_OUT27
CIC2_OUT28
CIC2_OUT29
CIC2_OUT30
CIC2_OUT31
CIC2_OUT32
CIC2_OUT33
CIC2_OUT34
CIC2_OUT35
CIC2_OUT36
CIC2_OUT37
CIC2_OUT38
CIC2_OUT39
CIC2_OUT40
CIC2_OUT41
CIC2_OUT42
CIC2_OUT43
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
End of Table 7-37
7.9 Interrupts
7.9.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6678 device are configured through the C66x CorePac Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through chip interrupt controller (CIC) blocks. This is clocked using CPU/6.
The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, plus
the EDMA3CC, CIC0, and CIC1 provide 17 additional events as well as 8 broadcast events to each of the C66x
CorePacs, CIC2 provides 26 and 24 additional events to EDMA3CC1 and EDMA3CC2 respectively, and CIC3
provides 8 and 32 additional events to EDMA3CC0 and HyperLink respectively.
There are a large number of events at the chip level. The chip level CIC provides a flexible way to combine and remap
those events. Multiple events can be combined to a single event through chip level CIC. However, an event can only
be mapped to a single event output from the chip level CIC. The chip level CIC also allows the software to trigger
system event through memory writes. The broadcast events to C66x CorePacs can be used for synchronization
among multiple cores or inter-processor communication purpose and etc. For more details on the CIC features,
162
Peripheral Information and Electrical Specifications
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