TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-29 shows the C6678 interrupt topology.
Figure 7-29
TMS320C6678 Interrupt Topology
98 Primary Events
17 Secondary Events
Core0
Core1
Core2
Core3
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
8 Reserved Secondary Events
5 Reserved Primary Events
89 Core-only Secondary Events
63 Common Events
CIC0
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
8 Broadcast Events from CIC0
98 Primary Events
17 Secondary Events
Core4
Core5
Core6
Core7
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
8 Reserved Secondary Events
89 Core-only Secondary Events
63 Common Events
5 Reserved Primary Events
CIC1
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
8 Broadcast Events from CIC1
38 Primary Events
63 Common Events
EDMA3
CC1
26 Secondary Events
9 Reserved Secondary Events
CIC2
40 Primary Events
EDMA3
CC2
88 EDMA3CC-only
Secondary Events
24 Secondary Events
32 Primary Events
HyperLink
17 Reserved Secondary Events
63 Events
32 Secondary Events
CIC3
8 Primary Events
EDMA3
CC0
8 Secondary Events
164
Peripheral Information and Electrical Specifications
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