欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320C6678XCYP25 参数 Datasheet PDF下载

TMS320C6678XCYP25图片预览
型号: TMS320C6678XCYP25
PDF下载: 下载PDF文件 查看货源
内容描述: 多核固定和浮点数字信号处理器 [Multicore Fixed and Floating-Point Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 242 页 / 2088 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320C6678XCYP25的Datasheet PDF文件第147页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第148页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第149页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第150页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第152页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第153页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第154页浏览型号TMS320C6678XCYP25的Datasheet PDF文件第155页  
TMS320C6678  
Multicore Fixed and Floating-Point Digital Signal Processor  
SPRS691D—April 2013  
www.ti.com  
Table 7-26  
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 3 of 3)  
(see Figure 7-19 and Figure 7-20)  
No.  
Min  
Max Unit  
4 (2) ps,RMS  
4 (2) ps,RMS  
5
5
tj(PCIECLKN)  
tj(PCIECLKP)  
Jitter, peak_to_peak _ periodic PCIECLKN  
Jitter, peak_to_peak _ periodic PCIECLKP  
End of Table 7-26  
1 See the Hardware Design Guide for KeyStone devices in ‘‘Related Documentation from Texas Instruments’’ on page 73 for detailed recommendations.  
2 The jitter frequency mask shown in the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 73 must also be met for  
the specific operating mode chosen.  
Figure 7-19  
Figure 7-20  
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing  
1
2
3
5
<CLK_NAME>CLKN  
<CLK_NAME>CLKP  
4
Main PLL Clock Input Transition Time  
peak-to-peak differential input  
250 mV peak-to-peak  
0
voltage (250 mV to 2 V)  
TR = 50 ps min to 350 ps max (10% to 90 %)  
for the 250 mV peak-to-peak centered at zero crossing  
7.6 DD3 PLL  
The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset,  
DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.  
DDR3 PLL power is supplied externally via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter  
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related  
Documentation from Texas Instruments’’ on page 73. For the best performance, TI recommends that all the PLL  
external components be on a single side of the board without jumpers, switches, or components other than those  
shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external  
components (C1, C2, and the EMI filter).  
Figure 7-21 shows the DDR3 PLL.  
Figure 7-21  
DDR3 PLL Block Diagram  
DDR3 PLL  
PLLD xPLLM /2  
0
1
DDRCLK(N|P)  
PLLOUT  
DDR3  
PHY  
BYPASS  
Copyright 2013 Texas Instruments Incorporated  
Peripheral Information and Electrical Specifications 151  
 
 
 
 复制成功!