TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-26
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 2 of 3)
(see Figure 7-19 and Figure 7-20)
No.
Min
Max Unit
3
4
tw(CORECLKP)
Pulse width _ CORECLKP low
0.45*tc(CORECLKP)
0.55*tc(CORECLKP)
ns
tr(CORECLK_250mv)
Transition time _ CORECLK differential rise time
(250mV)
50
50
350
ps
4
5
5
tf(CORECLK_250mv)
tj(CORECLKN)
Transition time _ CORECLK differential fall time (250mV)
Jitter, peak_to_peak _ periodic CORECLKN
Jitter, peak_to_peak _ periodic CORECLKP
SRIOSGMIICLK[P:N]
350
0.02*tc(CORECLKN)
0.02*tc(CORECLKP)
ps
ps
ps
tj(CORECLKP)
1
1
3
2
2
3
4
tc(SRIOSGMIICLKN)
tc(SRIOSGMIICLKP)
tw(SRIOSGMIICLKN)
tw(SRIOSGMIICLKN)
tw(SRIOSGMIICLKP)
tw(SRIOSGMIICLKP)
Cycle time _ SRIOSGMIICLKN cycle time
Cycle time _ SRIOSGMIICLKP cycle time
Pulse width _ SRIOSGMIICLKN high
Pulse width _ SRIOSGMIICLKN low
3.2 or 4 or 6.4
3.2 or 4 or 6.4
ns
ns
ns
ns
ns
ns
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)
0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)
Pulse width _ SRIOSGMIICLKP high
Pulse width _ SRIOSGMIICLKP low
tr(SRIOSGMIICLK_
250mv)
Transition time _ SRIOSGMIICLK differential rise time
(250 mV)
50
50
350
ps
4
tf(SRIOSGMIICLK_
250mv)
Transition time _ SRIOSGMIICLK differential fall time
(250 mV)
350
ps
5
5
5
tj(SRIOSGMIICLKN)
tj(SRIOSGMIICLKP)
tj(SRIOSGMIICLKN)
Jitter, peak_to_peak _ periodic SRIOSGMIICLKN
Jitter, peak_to_peak _ periodic SRIOSGMIICLKP
4 (2) ps,RMS
4 (2) ps,RMS
Jitter, peak_to_peak _ periodic SRIOSGMIICLKN (SRIO
not used)
8 (2) ps,RMS
8 (2) ps,RMS
5
tj(SRIOSGMIICLKP)
Jitter, peak_to_peak _ periodic SRIOSGMIICLKP (SRIO
not used)
HyperLinkCLK[P:N]
Cycle time _ MCMCLKN cycle time
Cycle time _ MCMCLKP cycle time
Pulse width _ MCMCLKN high
1
1
3
2
2
3
4
4
5
5
tc(MCMCLKN)
tc(MCMCLKP)
3.2 or 4 or 6.4
3.2 or 4 or 6.4
ns
ns
tw(MCMCLKN)
tw(MCMCLKN)
tw(MCMCLKP)
tw(MCMCLKP)
tr(MCMCLK_250mv)
tf(MCMCLK_250mv)
tj(MCMCLKN)
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
ns
ns
ns
ns
ps
ps
Pulse width _ MCMCLKN low
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
0.55*tc(MCMCLKP)
0.55*tc(MCMCLKP)
350
Pulse width _ MCMCLKP high
0.45*tc(MCMCLKP)
Pulse width _ MCMCLKP low
0.45*tc(MCMCLKP)
Transition time _ MCMCLK differential rise time (250mV)
Transition time _ MCMCLK differential fall time (250mV)
Jitter, peak_to_peak _ periodic MCMCLKN
Jitter, peak_to_peak _ periodic MCMCLKP
PCIECLK[P:N]
50
50
350
4 (2) ps,RMS
4 (2) ps,RMS
tj(MCMCLKP)
1
1
3
2
2
3
4
4
tc(PCIECLKN)
Cycle time _ PCIECLKN cycle time
3.2 or 4 or 6.4 or 10
3.2 or 4 or 6.4 or 10
0.45*tc(PCIECLKN) 0.55*tc(PCIECLKN)
ns
ns
tc(PCIECLKP)
Cycle time _ PCIECLKP cycle time
tw(PCIECLKN)
tw(PCIECLKN)
tw(PCIECLKP)
Pulse width _ PCIECLKN high
ns
ns
ns
ns
ps
ps
Pulse width _ PCIECLKN low
0.45*tc(PCIECLKN)
0.45*tc(PCIECLKP)
0.45*tc(PCIECLKP)
50
0.55*tc(PCIECLKN)
0.55*tc(PCIECLKP)
0.55*tc(PCIECLKP)
350
Pulse width _ PCIECLKP high
tw(PCIECLKP)
Pulse width _ PCIECLKP low
tr(PCIECLK_250mv)
tf(PCIECLK_250mv)
Transition time _ PCIECLK differential rise time (250 mV)
Transition time _ PCIECLK differential fall time (250 mV)
50
350
150
Peripheral Information and Electrical Specifications
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