TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-21
Reset Control Register (RSTCTRL) Field Descriptions
Bit
Field
Description
31-17 Reserved
Reserved.
16
SWRST
Software reset
0 = Reset
1 = Not reset
15-0
KEY
Key used to enable writes to RSTCTRL and RSTCFG.
End of Table 7-21
7.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL Controller’s
RSTCTRL Register; i.e., a hard reset or a soft reset. By default, these resets will be hard resets. The Reset
Configuration Register (RSTCFG) is shown in Figure 7-15 and described in Table 7-22.
Figure 7-15
Reset Configuration Register (RSTCFG)
31
14
13
12
11
4
3
0
(1)
Reserved
R-0
PLLCTLRSTTYPE
R/W-0 (2)
RESETTYPE
R/W-02
Reserved
R-0
WDTYPE[N
R/W-02
]
Legend: R = Read only; R/W = Read/Write; -n = value after reset
1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)
2 Writes are conditional based on valid key. For details, see Section 7.5.2.7 ‘‘Reset Control Register (RSTCTRL)’’.
Table 7-22
Reset Configuration Register (RSTCFG) Field Descriptions
Bit
Field
Description
31-14 Reserved
Reserved.
13
PLLCTLRSTTYPE PLL Controller initiates a software-driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12
RESETTYPE
RESET initiates a reset of type:
0 = Hard reset (default)
1 = Soft reset
11-4
Reserved
WDTYPE3
WDTYPE2
WDTYPE1
WDTYPE0
Reserved.
3
2
1
0
Watchdog timer [N] initiates a reset of type:
0 = Hard reset (default)
1 = Soft reset
End of Table 7-22
7.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non
power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current
values of PLL multiplier, divide ratios and other settings. Along with setting module specific bit in RSISO, the
corresponding MDCTLx[12] bit also needs to be set in PSC to reset isolate a particular module. For more
information on MDCTLx register see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related
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Peripheral Information and Electrical Specifications 147
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